| 摘要 |
<p>PURPOSE:To provide the circuit in which error correction is correctly implemented regardless of a simple circuit configuration of a majority decision circuit only. CONSTITUTION:A 1st counter 15 uses a control signal of a MUSE signal as an enable signal and uses a field signal as a reset signal and outputs plural bits as position data. A control signal decode circuit 16 detects an address based on the result. A majority decision circuit 19 takes majority decision by counting prescribed data from a data input terminal 10 for plural number of times based on the prescribed address from the control signal decode circuit 16. The majority decision circuit 19 outputs a 2nd bit as a control signal by allowing 2-bit counters to act like a so-called majority decision circuit in which an output '0' or '1' among outputs '0', '1', '2', '3' is at '0 or L level' and an output '2' or '3' is at '1 or H level'.</p> |
