| 摘要 |
PURPOSE:To provide a high speed operation by providing plural shift circuits, which shift for a prescribed clock number, and corresponding pairs of selector, directly connecting one side of the signal input terminal to a digital data input terminal and connecting the other side to before and selector behind output terminal through pair of shift circuits. CONSTITUTION:A digital data input terminal 10 and an output terminal 11 are connected through the upper side of the input and output sides of a selector 41. Moreover, the terminal 11 and the lower side of the input side of the selector 41 are connected through the upper side of the input output side of a selector 42 and a shift circuit 71. Similarly, in a lowest stage circuit, the terminal 10 and the lower side of the input output side of a selector 47 are connected through a shift circuit 77. Thus, the selector 41 and the shift circuit 71, 42 and 72, 43 and 73, 44 and 74, 45 and 75, 46 and 76 and 47 and 77 are made into pairs, respectively. Moreover, D0 to D2, which set the amount of delay, are connected to the set terminal side of the selectors 41 to 47 which belong to SA to SF decode outputted through a decode circuit 60. |
