| 摘要 |
PURPOSE:To make it possible to execute operation in parallel with the input of a signal by successively setting up different time sections so that a time section allowed to analyze a time sequential signal maintains a prescribed length and then executing the processing of the time sequential signal. CONSTITUTION:A clock signal CLK, a reset signal RESET and a synchronizing analysis-permitted signal w(t) are inputted to a control circuit 1. Signals included within the time sections allowed to execute analysis of time sequential signals A(t) are successively inputted to a delay means such as a shift register 21 to obtain delay signals B(t), an effective difference signal C(t) is found out by a differential operation means in each input of the signal included in the analysis-permitted time section and the difference signals C(t) are accumulated to find out an accumulation signal D(t). Consequently the short-time average value of signals in the analysis-permitted sections of the signals A(t) is found out as the signal D(t) and the signal D(t) can be successively outputted while successively inputting the signals A(t). |
