| 摘要 |
PURPOSE:To provide the variable delay circuit in which a sufficient logic level is ensured and the delay time is changed precisely. CONSTITUTION:The circuit is provided with a buffer circuit B receiving an input signal, plural exclusive OR circuits X-1-X-n receiving the said input signal to one input, an adder circuit A summing outputs of the exclusive OR circuits X-1-X-n and outputting the sum, and plural capacitors C coupling an output of the adder circuit A and an output of the buffer circuit B. A delay time control signal fed to the other input of the exclusive OR circuits X-1-X-n is transited independently in a range between a prescribed high level and a low level. |
