| 摘要 |
PURPOSE:To suppress the deterioration of window margin due to the fluctuation of temperature, power supply voltage, and secular change and to increase the reliability of data reading. CONSTITUTION:A PLL circuit 1 makes a clock signal 103 from read data 101, which is supplied to a delay circuit 2, generating a plurality of delay clock signals TD (k) with dissimilar phases. These delay clock signals TD (k) are given to a multiplexer 10, and a microprocessor 6 selects a delay clock signal TD (k) according to the data stored in a register 11 to be supplied to a latch circuit 3. The latch circuit 3 latches the read data 101 by means of the clock signal TD (k) which is decoded by a decoder 4, and read errors are detected by a disk controller 5. When a read error is detected, a retrying operation is performed to change the data of the register 11, eliminating read errors. |
