Bit-verschachtelter Multiplexer mit Byte-Synchronisation für verbindende Geräte.

摘要

A bit interleaved multiplexer system (10) permitting byte synchronization of apparatus (20a,20b,...) communicating thereon without the consumption of additional aggregate bandwidth is provided. The system comprises a multiplexer (30), a demultiplexer (40), and an aggregate line (50a). The multiplexer (30) includes a transmit frame (52) which includes a memory means and at least one recirculating counter which is programmed according to a framing algorithm, and a transmit data buffer (54) and transmit mark buffer (56) for each terminal (20a,20b,...) which is to be connected to the system (10). Every time the transmit frame (52) requests a predetermined bit of a byte (e.g. an MSB), a "1" is marked in teh mark buffer (56). When a bit leaves the mark buffer (56) it causes the terminal (20a,20b,...) to write a bit into the transmit data buffer, with the written bit being an MSB when the bit leaving the mark buffer (56) is a "1". By arranging the delay through the transmit mark and data buffers (54,56) to be equal to I(L) + C, where I is an integer greater than zero, L is the length of a byte, and C is a contant phase shift, when the transmit frame (52) requests an MSB, an MSB will be sent by the transmit data buffer C requests later. If C is set to zero, an MSB will be sent when the transmist frame (52) so requests. The demultiplexer (40) of the invention includes a receive frame (62) which is synchronized with the transmit frame (52) and which includes a memory means and at least one recirculating counter, and a receive data buffer (64) and receive mark buffer (66) for each terminal (20a,20b,...) which is connected to the system. Every time the framing algorithm indicates the M&B is being received by the receive frame, a "1" is marked into the receive mark buffer (66) while the bit is forwarded to the receive data buffer (64). Because the receive mark and receive data buffers (64,66) are equal in length, the terminal (20a,20b,...) receiving information from the buffers (64,66) will be provided with the information as to whether the received bit is an MSB.