发明名称 LAYOUT OF SIGNAL LINE IN THE SEMICONDUCTOR IC
摘要 This is about the signal line setting method of semiconductor integrated circuit, specially about one which blocks the influence of noise by the parasitic capacitance. This method applies to a case without needing the device line connected to device(40). The signal line area is shown by discerning the first, the second and the third stages (41)(42)(43) in the order of distance away from the driver(4). The signal line area in the first stage(41) arrayed in the state at the first interval(s1), and the second stage is at the second interval ,and the third stage is at the third interval. The interval of the first, the second and the third have the characteristic as s1<s2<s3.
申请公布号 KR930009575(B1) 申请公布日期 1993.10.07
申请号 KR19900020285 申请日期 1990.12.11
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 LEE, JONG - RYOL
分类号 H01L27/10;(IPC1-7):H01L27/10 主分类号 H01L27/10
代理机构 代理人
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