Semiconductor memory apparatus having reduced amount of bit line amplification delay

摘要

In a DRAM formed of MOS FETs, respectively different values of substrate bias voltage are applied to transistors of different types of circuit in accordance with the circuit functions, to thereby enable the threshold voltage of the transistors of the sense amplifiers to be brought close to zero, thereby reducing the bit line amplification delay, while maintaining sufficiently high values of threshold voltage for other circuits.