| 摘要 |
A low power logic array and a programmable logic device made up of two successive logic arrays, at least one of which being a low power array, in which the programmable elements in the array are multibit memory elements. Logic gates combine the outputs of corresponding memory elements. The logic array includes a set of array inputs which may be arranged in groups connecting to decoder inputs. Decoder outputs provide an address signal to address inputs of the memory elements. In a preferred embodiment, the memory elements are arranged in a matrix of rows and columns with each row connected to a decoder and each column coupling to one or more logic gates. The logic gates may be AND, OR, NAND or NOR gates, and may be arranged in a hierarchy of successive stages of logic gates.
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