| 摘要 |
<p>The present invention discloses a semiconductor memory device comprising a plurality of memory cell arrays (MCA0 to MCA3), a plurality of decoders (RD0 to RD3) for decoding a first address of memory addresses, each of the decoders (RD0 to RD3) being connected to a corresponding memory cell array, a plurality of sense amplifiers (SA0 to SA3), each connected to a corresponding memory cell array, a decoder (CD) for decoding a second address of the memory addresses, the decoder (CD) being connected to every memory cell array (MCA0 to MCA3), to be shared by every memory cell array (MCA0 to MCA3), a plurality of redundancy memory cells (RM), each of which is arranged for a corresponding memory cell array, a plurality of programming circuits (PC0 to PC3), each arranged relative to a corresponding memory cell array to receive the first memory address and output a signal of a predetermined logic level corresponding to a defective memory cell in a memory cell array, and a programmable decoder (PD) for receiving the second address and signal from the programming circuits (PC0 to PC3), for changing a decoding state of the second address according to the logic level of the output signal from the programming circuits (PC0 to PC3) and for outputting a redundancy memory cell select signal which selects a redundancy memory cell in place of a specified defective memory cell. <IMAGE></p> |
