Microprocessor with hardware controlled power mangement and selectable input/output control pins.

摘要

A data processing device includes a plurality of subcircuits and circuitry for generating clock signals thereto. Detection circuitry detects the assertion of a control signal and disabling circuitry is operable to disable the clock signals to one or more of the subcircuits responsive to the control signal. In addition, circuitry is provided for selectively decoupling one or more subcircuits with associated input/output pins such that pins asociated with enhanced features may be decoupled to provide comptability with a desired microprocessor architecture.