| 摘要 |
<p>A rounding operation circuit for arithmetic logic means of a signal processor provided for counting fractions over 1/2 as one and disregarding the rest for the positive and negative number, which comprises a decoder circuit (3) having an (n+ 1)-long input to which a first input signal (1) represented by two's complement and a second n-bit long input signal (2) for specifying the rounded position of the first signal are entered, when the first input signal is positive, a signal in which the bit at the rounded position is "1" and the rest is "0" is emitted based on the second input signal and, when the first input signal is negative, a signal in which the bits less significant than the bit at the rounded position are all "1" and the rest is "0" is emitted; arithmetic logic means (6) for adding the output signal (4) of this decoder circuit and the first input signal; and a rounding-down circuit (8) for counting 1 and cutting away 0 positively and negatively symmetrically to any rounding position, to allow a fast and accurate rounding operation. <IMAGE></p> |
