| 摘要 |
PURPOSE: To solve data dependence among plural instructions in a storage device like a reorder buffer. CONSTITUTION: Each time the destination indicator of the instruction first stored in the storage device is matched with a source indicator in the instruction to be next sent, a comparator circuit 42 generates a comparison hit signal D. A 1st enable circuit 66 generates a 1st enable signal C for the instruction of a 1st packet specified by read and write pointers. Concerning the match of the comparison hit signal D and the 1st enable signal C, a 1st AND circuit 50 generates a hit enable signal E. Concerning the instruction of a 2nd packet specified by the read pointer and the hit enable signal E, a 2nd enable circuit 80 generates a 2nd enable signal F. Concerning the match of the 2nd enable signal F and the hit enable signal E, a 2nd AND circuit 86 generates an output signal G. |
