| 摘要 |
PURPOSE:To omit the setting jobs of the total bit number and the invalid bit number which are included in a single word. CONSTITUTION:The output of the signals held in a shift register 15 is started at the changing point of the input word/clock signal IWC which is synchronous with an input signal IN. Then the changing point of the output word/clock signal OWC signal set at a point where the rise or fall changing point of the bit clock signal BC just equal to the valid bit number NVB is recognized from the changing point of the signal IWC. The output of the valid bits is complete by the setting timing of the changing point of the signal OWC. The output of the invalid bits is carried on until the next changing point of the signal IWC. Thus it is possible to omit the setting jobs of the total bit number and the invalid bit number. |
