Selectively locking memory locations within a microprocessor's on-chip cache
摘要
A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also includes the capability for locking instruction cache entries without requiring that the instructions be executed during the locking process.
申请公布号
US5249286(A)
申请公布日期
1993.09.28
申请号
US19920982031
申请日期
1992.11.24
申请人
NATIONAL SEMICONDUCTOR CORPORATION
发明人
ALPERT, DONALD B.;OZ, OVED;INTRATER, GIDEON;MARKO, REUVEN;SHACHAM, ALON