发明名称 Solder finishing planar leaded flat package integrated circuit leads
摘要 Apparatus (10) and method for solder finishing the leads of an integrated circuit package are applicable to "flat packs" or flat packages having coplanar rows of leads (84) along sides of the flat package (75). First and second tracks (22,26) are formed with elongate first and second supporting surfaces (72,74) oriented with the first and second supporting surfaces at opposite first and second downwardly depending angles ( THETA 1, THETA 2). First and second index edges (70) are formed along the respective first and second supporting surfaces of the first and second tracks (22,26) for retaining a flat package (75) at the respective opposite first and second downwardly depending angles. Vertical first and second falling columns of molten solder are established at first and second loci of solder finishing (16a,16b) defined by solder bridge sections (66,68) with the first and second falling columns (85) located on the lower sides of the respective first and second tracks (22,26). A conveyor line (44) formed with pushers (76) pushes the flat package on the respective first and second tracks (22,26) along first and second transport paths (25,28) with respective downwardly depending first and second rows of leads (84) passing through the respective first and second tilting mechanism (100) at the transfer end of the track section lifts the flat package from the first track (22), reorients the flat package from the first downwardly depending angle ( THETA 1) to the second downwardly depending angle ( THETA 2) and deposits the flat package (75) on the second track (26).
申请公布号 US5248520(A) 申请公布日期 1993.09.28
申请号 US19920835208 申请日期 1992.02.13
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 WOOD, RICHARD C.;DOHERTY, ROGER H.
分类号 B23K1/00;C23C26/02 主分类号 B23K1/00
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