| 摘要 |
PURPOSE:To make a PLL circuit single by constituting the PLL circuit which generates a reference clock whose oscillating efficiency is high, which is synchronized with a video signal at a high speed even when the video signal is standard or non-standard, at the time of preparing the reference clock synchronized with the inputted video signal, and supplying it to a picture processing system, in a picture processor. CONSTITUTION:A horizontal synchronizing signal 8 obtained from a synchronizing separator circuit is compared with a signal 12 frequency-divided by a frequency dividing circuit 4 by a phase comparator circuit 2, based on a reference clock signal being the output of a voltage control oscillator 3. Then, when the phase difference of the two signals is more than a constant value, a braking signal 9 outputted from a control circuit 5 is outputted as an inhibiting signal, transmitted through a gate circuit 7, and a frequency-dividing operation is stopped. When the next horizontal synchronizing signal 8 arrives, the braking signal 9 is changed to a permitting signal. As the result, the frequency-dividing circuit 4 resumes the frequency-dividing operation, and the synchronizing operation is attained. |
