发明名称 MICROPROCESSOR HAVING A VARIABLE LENGTH INSTRUCTION FORMAT
摘要 PCT No. PCT/JP90/00034 Sec. 371 Date Jun. 22, 1990 Sec. 102(e) Date Jun. 22, 1990 PCT Filed Jan. 12, 1990 PCT Pub. No. WO90/08355 PCT Pub. Date Jul. 26, 1990.Microprocessor for executing variable length instructions including the basic areas having the instruction code and operand designation area with the extensible area to be added in accordance with designation of the basic areas for extending the operand designation areas. It includes a basic area decoder for identifying the existence or non-existence of the successive basic areas and extensible areas and for outputting the basic areas transition request or extensible area transition request by decoding the basic area, an extensible area decoder for identifying the existence or non-existence of the continuation of the extensible areas and for outputting an extensible area continuation request by decoding the extensible area, and a decoder sequencer for controlling the two decoders in accordance with a predetermined sequence. The sequencer comprises a first control circuit for generating a control signal for the basic area decoder responding to the basic area transition request, a second control circuit for generating a control signal for the extensible area decoder responding to the extensible area transition request or the extensible area continuation request and a third control circuit connected to the first and second control circuits for delaying operations of the first control circuit corresponding to the basic area transition request in case the extensible transition request or extensible area continuation request is issued.
申请公布号 US5249273(A) 申请公布日期 1993.09.28
申请号 US19900499432 申请日期 1990.01.12
申请人 FUJITSU LIMITED 发明人 YOSHITAKE, AKIHIRO;OHSHIMA, TOSHIHARU
分类号 G06F9/30;(IPC1-7):G06F9/06;G06F9/34 主分类号 G06F9/30
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