| 摘要 |
PURPOSE:To perform the retrial of data reading when the intermittent failure of the peripheral circuit of a CPU and a data reading fault caused by external noise occur. CONSTITUTION:The instruction code reading retrial circuit is composed of a CPU 1 having a pipeline structure, a main cache memory means 7 providing cache memory, a sub-cache memory means 9, a memory access interpretation means 4 interpreting the type of a memory access, a cache switch means 8 performing the switch of the main/sub-cache and generating a flashing signal, a parity inspection means 3 inspecting whether data is normally read by the read of the memory or not and notifying the CPU 1, a type holding means and a cache flash means of the generation of parity at the time of the decision of an error, the type holding means holding type information and a pointer restoration means 6 restoring an execution address pointer (IP) to a point of time when a NMI generates when the interpretation result of the type holding means at the time of the decision of the error is the type of the instruction code. |
