| 摘要 |
PURPOSE:To obtain a master-slice IC device, through which a logic circuit in which the lowering of load driving capacitance with the increase of inputs is prevented can be realized, by reducing the number of elements required per the number of inputs and driving the whole outputs through a composite inversion buffer consisting of a bipolar and a CMOS. CONSTITUTION:The number of inputs to a cell 10 is increased only by NMOSFETs Q2c-Q2f. Since feed through currents are generated at that time, source-drain terminals 118, 119 for a PMOSFETQ1b for precharge, source-drain terminals 116, 117 for an NMOSFETQ2b for discharge and clock signal input terminals 103 are fitted, and currents are inputted to gates for the Q1, Q2, thus dynamic-operating a device. When the number of inputs is increased, the number of cascade connections of NMOSFETs is augmented and the resistance of input steps is elevated, thus reducing base currents in bipolar elements Q3a, Q3b at output steps. Consequently, the input steps and the output steps are separated, and the output steps are constituted by inverters, thus preventing effects. A logic circuit consisting of four inputs to the Q2c-Q2f can be constituted by selective connections, the logic circuit such as a NOR with a bipolar CMOS composite type inversion buffer is obtained, and only one is increased as elements. |
