Semiconductor memory device with high speed write operation

摘要

A dynamic RAM for performing high speed write operation after performing read operation. The inventive device receives write data after pre-charging and equalizing a pair of bit lines, by using a equalization signal activated for a predetermined time, at a time point at which a write enabling signal begins to be activated. Provided between the bit lines is an equalization circuit having an NMOS transistor of which gate is connected to the equalization signal depending on the write enabling signal.