| 摘要 |
<p>PURPOSE:To reduce data transmission time, by dividing a first and a second bonding pad column into two short columns, and arranging an inner circuit and a data bus so as to correspond with said columns. CONSTITUTION:Each of the data I/O pad columns P101-04 and P105-08 on the left side and the right side of a semiconductor substrate 20 are divided into two short columns which are adjacent to each other. Inner circuit regions 21a-21f containing memory cell array parts 211a-211f and column selection data transfer circuits 212a-212f, and data buses 22a-22f are arranged (21c, 22c/21d, 22d/21e, 22e/21f, 22f) so as to correspond with four short columns of the data I/O pad pairs P101.P102/P103.P104/P105.P106/P107.P108. Data I/O buffer circuits B101-08 also are arranged (B101.B102/B103.B104/B105.B106/B107.B108) so as to correspond with the short columns. Writing and readout of data are performed with bit parallel code word unit corresponding with the short columns of the data I/O pads. Thereby data transmission time is shortened.</p> |
