发明名称 TIMING EXTRACTION METHOD AND CIRCUIT
摘要 PURPOSE:To attain the integration by using a digital circuit to construct a timing extracting circuit which receives a burst signal and then demodulates it. CONSTITUTION:This circuit is constituted of a timing generating circuit 22 for outputting the timing signals in the same cycle as the clocks of the received signals, a signal detecting circuit 24 which detects the data signals out of the received signals by the timing signals of the circuit 22, an A/D converter 21 which samples the received signals in the different cycles from the clocks of these received signals and converts these signals into the digital ones, an envelope detection circuit 23 which applies the envelope detection to the received signals digitized by the converter 21 and acquires the envelope signal data, and a CPU 25 serving as a correction circuit which corrects the phase outputted from the circuit 22 based on the phase error produced between the proper signal detection timing information acquired from the envelope signal data given from the circuit 23 and the present signal detection timing.
申请公布号 JPH05244137(A) 申请公布日期 1993.09.21
申请号 JP19920043776 申请日期 1992.02.28
申请人 CASIO COMPUT CO LTD;SOGO TSUSHIN ENG KK 发明人 TSUCHIDA MASAHIKO;KORI TAKEJI
分类号 H04L7/02 主分类号 H04L7/02
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