| 摘要 |
PURPOSE:To shorten the simulation time of the fault simulation device. CONSTITUTION:A selecting circuit 20 selects the positive of a gate and the event of a fault. An input state memory 60 stores information on the input state of the gate. A fault setting circuit 70a sets the fault. A gate attribute memory 80 stores the kind of logical operation. A level control memory 50 stores level control data in simulation, level by level. An arithmetic circuit 90a performs the simulation. An output state memory 110 stores the output value of positive simulation. A positive event generation check circuit 120 compares the result of the positive simulation with the last result to check the generation of a positive event. An FIFO 130 stores a positive event and an FIFO l40a stores a fault event. A connection information storage memory 150 stores the connection destination of the gate. A propagated data generating circuit 160 generates propagated data to the connection destination. An FIFO 170 stores the propagated data in order. A transfer circuit 180 reads the stored data out and transfers them to the connection destination of the gate. |
