| 摘要 |
<p>PURPOSE:To provide the data synchronizing circuit which can be applied to an efficient data transmission executed by the smallest number of interface signal lines. CONSTITUTION:Clocks A-D whose phases are different from each other are supplied to latches 11-14, and by a rise of these clocks, receiving data is respectively latched and outputted. These latch outputs are supplied to a phase discriminating part 16, a variation of a value of the latch outputs is respectively monitored in the part 16, and an optimal latch output which follows the variation of the value of the receiving data is discriminated, and a selecting signal is supplied to selecting parts 17, 18. The selecting part 17 selects the optimal latch output, based on the selecting signal, supplies it to a frame phase-locked circuit 2, executes a frame pattern, and the selecting part 18 selects a clock signal of an optimal phase, based on the selecting signal, supplies it to a bit buffer 4, and extracts only data, based on the frame pattern.</p> |
