| 摘要 |
PURPOSE:To simultaneously activate plural test modes employing a minimum number of control signals. CONSTITUTION:Test mode activating signals OPT1 to 0PT4 are generated by decoding address signals A1 and A2 by a decoding circuit 3 and held in a flip-flop 4. While a super voltage is being applied, the latch condition is not released even when a CBR cycle is executed and plural test modes are specified if the address signals A1 and A2 are changed. |
