发明名称 ATM/STM CONVERSION CIRCUIT
摘要 <p>PURPOSE:To economically absorb fluctuation with a short delay time in the ATM/STM conversion circuit used for terminals housed in the ATM network and to provide the ATM/STM conversion circuit minimizing the jitter of de- celled signals. CONSTITUTION:The circuit used for the de-cell processing section of the ATM/ STM conversion for information on voice and pictures in the terminals housed in the ATM network is provided with a buffer 50 having the double capacity of the maximum fluctuation time in the ATM network and a read control section 60 comparing the set threshold value with the number of cells in the buffer 50 and controlling the read of the buffer 50. After the arrival of the first cell, the read control section 60 reads the content of the buffer 50 in succession in the lapse of the maximum delay time in the ATM network.</p>
申请公布号 JPH05244186(A) 申请公布日期 1993.09.21
申请号 JP19910196486 申请日期 1991.08.06
申请人 FUJITSU LTD 发明人 KATO TSUGIO;SHIMOE TOSHIO;KATO YUJI;TOMONAGA HIROSHI
分类号 (IPC1-7):H04L12/48 主分类号 (IPC1-7):H04L12/48
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