| 摘要 |
PURPOSE:To eliminate the reduction of the transmission efficiency and to improve the reliability of a frame synchronizing system by deciding the settlement of the frame synchronization after the input of a 2nd frame multiplex signal which is delayed by prescribed extent by a delay circuit and a 1st frame multiple signal. CONSTITUTION:The frame synchronizing signal and the multiplex signal 101 of the single series which is multiplexed by an additional bit, etc., used for error correction are inputted to an error correcting decoder 1 and a frame synchronizing circuit 4. The signal 101 inputted to the decoder 1 is inputted to an arithmetic circuit 2 and a delay circuit 3 respectively, and an input signal 101A delayed by an extent equal to the arithmetic time of the circuit 2 is outputted. Then the circuit 4 produces a multiplex signal 105 delayed by a prescribed time by a relay circuit 6 as well as the signal 101. Then the frame synchronizing signal included in the multiplex signal of the double series of the present frame synchronizing signal 101 and the delayed multiplex signal 105 are monitored so that the frame synchronization is settled. |
