发明名称 Code error correction apparatus
摘要 A product code block generated by adding an outer code block and an inner code block to digital information signal arranged in matrix is received at least twice by a code error correction apparatus. In decoding the first received product code block by use of an inner code parity, an error flag is set for an inner code block having an uncorrectable error by an inner code parity. In decoding the second received product code block by use of an inner code parity, the error flag is referrenced so that an inner code block that could be correctly decoded or corrected in the second decoding of all the inner code blocks having an uncorrectable error in the first decoding is replaced by the second inner code block. Also, the check information such as a check sum is generated and stored each time of receiving, and an error flag is set for even an inner code block that could be corrected in either the first or second decoding, if the check sums for them fail to coincide with each other.
申请公布号 US5247523(A) 申请公布日期 1993.09.21
申请号 US19900551009 申请日期 1990.07.11
申请人 HITACHI, LTD. 发明人 ARAI, HIDEO;NISHIMURA, KEIZO;INOUE, YASUYUKI
分类号 G06F11/10;H03M13/03;H03M13/29 主分类号 G06F11/10
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