| 摘要 |
PURPOSE:To realize a CMOS logic circuit provided with a delay circuit from a few number of elements by connecting a Schottky barrier diode to an output terminal with a resistor connected in parallel between the anode and cathode connected. CONSTITUTION:This semiconductor integrated circuit is constituted by connecting the Schottky barrier diode SBD with a resistor R parallel-connected to the output terminal 6 between the anode and cathode of the CMOS logic circuit 10 which is constituted of MOS transistors Q1 to Q4 and executes 2-input NOR logical operation for input signals D3, D4 to signal input terminals 3, 4 by connecting its anode to the output terminal 5. Propagation delay time in the case that an output signal D5 changes from a high level to a low level is nearly equal to the propagation delay time of the CMOS logic circuit 10. On the other hand, the propagation delay time in the case that it changes from the low level to the high level becomes the sum of the delay time of the CMOS logic circuit 10 and the delay time at the resistor R as a delay element, and the propagation delay time can be made longer at only the rise of output. |
