| 摘要 |
A constant output circuit wherein outputs are not a function of deviations of reference voltage. More specifically, the outputs maintain their logic "1" and logic "0" values, even when there are reference voltage noise or fluctuation in the circuit. This constant output circuit having a logic "1" output node and a logic "0" output node comprises a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor. A logical inversion operation is performed between a first input node and a first output node of a logic circuit. The first input node is coupled to the logic "1" output node. The gate of said first PMOS transistor is coupled to the first output node of the logic circuit, the source to the power supply, and the drain to said logic "1" output node. The gate of said second PMOS transistor is coupled to the logic "1" output node, the source to the power supply, and the drain to said logic "1" output node. The gate of said first NMOS transistor is coupled to said logic "1" output node, the source to the ground, and the drain to said logic "0" output node. With this circuit design, the output values of logic "0" and logic "1" will not be affected by noises of the ground or the power supply of the circuit.
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