Watchdog circuit for parallel redundant processors e.g. for anti-blocking systems - has watchdog counters for each processor that provide combined output for counter generating combined signal.

摘要

Watchdog signals (WD1, WD2) are fed to the input parts of counters, (3a, 3b) and the output state is maintained so long as there is no input on the reset part (R). A pulse sequence is fed to the inputs of AND gates (7a, 7b) connected to the reset part. The pulses are transmitted to the resets until a specific counter state is reached e.g. 23. When a watchdog signal line goes high the count cycle begins and the counter output goes high at a specific state e.g. 22, and goes low when the reset point is reached. Both counters operate in the same way and a general reset is produced (8) for a counter (9) indicating that both are operating correctly. USE/ADVANTAGE - Provides continuous check that both processors are operating correctly.