| 摘要 |
The circuit provents the transfer of the abnormal oscillating clock to the inner logic. The circuit includes the noise transfer prevention section (33) for connecting the source of the P-MOS transistors (21,24,27,28) and the drain of the N-MOS transistors (14) to the voltage (Vcc) to ground the source of the N-MOS transistors (23,26,32) and the drain of the P-MOS transistor (20) and a terminal of the capacitors (15,18) and connect the node (5) of the oscillating section (34) to the gate of the N-MOS transistors (14,17,30) and the P-MOS transistor (27), and connect the drain of P-MOS and N-MOS transistors (27,28),(30) to the input terminal of the function block (13).
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