| 摘要 |
PLL synthesizer circuitry comprises a phase comparator 3 which produces output signals phi R and phi P on the basis of a reference signal fr, output from a reference frequency divider 2, and a comparison signal fp output from a comparison frequency divider 4; the output signals phi R and phi P are negatively fed back to the comparison frequency divider 4 through a charge pump 5, a low-pass filter 6 and a voltage control oscillator 7, and a lock detection circuit 8 outputs a lock signal LD when in a locked state. When an output signal SVCO of the voltage control oscillator 7 coincides with a set frequency, when the lock detection circuit 8 does not output the lock signal LD, a reset circuit 15 outputs a reset signal PC to the reference frequency divider 2 and to the comparison frequency divider 4, and the reset signal PC brings the phase of the reference signal fr into conformity with the phase of the comparison signal fp. Such circuitry can shorten lock-up time without reducing unacceptably a time constant of a low-pass filter of the circuitry. <IMAGE> |
