<p>A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion (11). The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes (5) and continuous horizontally disposed program (22) and recall (18) gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride (7). The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention. <IMAGE></p>
申请公布号
EP0560069(A1)
申请公布日期
1993.09.15
申请号
EP19930102046
申请日期
1993.02.10
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
BERGENDAHL, ALBERT STEPHAN;BERTIN, CLAUDE LOUIS;CRONIN, JOHN EDWARD;KALTER, HOWARD LEO;KENNEY, DONALD MCALPINE;LAM, CHUNG HON;LEE, HSING-SAN