发明名称 |
Method for fabricating a poly emitter logic array and apparatus produced thereby |
摘要 |
A Schottky diode includes a metal layer (62) on an epitaxial region (24). The metal layer (62) is covered with a dielectric layer (64). An area (90) on the metal is exposed by opening a via (68) in the dielectric. The exposed area (90) is spaced from a buried perimeter (92) of the metal layer (62). A conductive lead (86) is formed in the Schottky via (68). A poly emitter terminal (46) connects a small sized emitter (50) formed in an epitaxial region (24) to the exterior. Poly emitter (46) presents a large area (76) to the exterior for alignment with a via (66) through a passivating dielectric layer (64), thus alleviating alignment problems.
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申请公布号 |
US5244832(A) |
申请公布日期 |
1993.09.14 |
申请号 |
US19890348342 |
申请日期 |
1989.05.05 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
MORRIS, FRANCIS J.;EVANS, STEPHEN A. |
分类号 |
H01L27/06;H01L21/285;H01L21/331;H01L21/338;H01L21/82;H01L21/8222;H01L23/532;H01L27/082;H01L27/118;H01L29/73 |
主分类号 |
H01L27/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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