| 摘要 |
In the case of setting one comparison timing in one operation period, a select signal is set to the "0" level, by which first, second and third counters are each put in the state of operation of a 1-to-4 frequency dividing counter which produces four frequency-divided outputs sequentially displaced apart in phase in a cyclic order. A first comparison clock is frequency divided by the first counter and its four frequency-divided outputs are used to latch a comparison signal in four first latch circuits in a sequential order, by which the comparison signal is demultiplexed and expanded. A first system clock is frequency divided by the second counter down to 1/4 and its four frequency-divided outputs are used to latch an expected value signal in four second latch circuits in a sequential order, by which the expected value signal is demultiplexed and expanded. The corresponding ones of the outputs from the first and second latch circuits are subjected to logical comparison by four comparators. A second system clock is frequency divided by the third counter down to 1/4 and its four frequency-divided outputs are used to time division multiplex the outputs of the four comparators one after another to obtain comparison result data of the same data rate as that of the input comparison signal. With some modification, it is also possible to set two comparison timings in one operational period.
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