发明名称 Apparatus for multiplying operands
摘要 In an apparatus and method for computing inverses and square roots a highly accurate initial approximation is computed using a second order polynomial equation, the coefficients of which are stored in a ROM. The most significant bits of an operand are used to address a ROM to select coefficients, providing different coefficients for different operand ranges. The remaining lesser significant operand bits are used in the computation; the coefficient values already account for the bits used to address them. The result is in single precision accuracy. For double precision, the polynomial results are used as the first approximation for a Newton-Raphson iteration. The multiplier has a split array mode to speed up the calculation of the polynomial, whereby two lesser precision values can be computed at once. The size of the coefficients is tailored to produce the proper precision result for each of the elements of Ax2+Bx+C. Separate values for the coefficients A, B, and C must be stored for the 1/x approximation and for the 1/ 2ROOT x approximation. Also to speed up the multiplier, the multiplier can accept one operand in carry/save format, by providing Booth recoder logic which can accept operands in a normal binary or in a carry/save format. Also employed is a rounding technique which provides IEEE exact rounding by an operation that includes only one multiplication.
申请公布号 US5245564(A) 申请公布日期 1993.09.14
申请号 US19910698758 申请日期 1991.05.10
申请人 WEITEK CORPORATION 发明人 QUEK, S. M.;HU, LARRY;PRABHU, JNYANESHWAR P.;WARE, FREDERICK A.
分类号 G06F7/52;G06F7/552;G06F17/11 主分类号 G06F7/52
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