发明名称
摘要 According to an image memory address assignment system, a frame memory is divided into a plurality of blocks. Upper bits of the address of the frame memory constitute a block address, and lower bits constitute an intrablock address. The block address is supplied to an address converter. The address converter has a conversion pattern ROM. The conversion pattern ROM stores conversion patterns each converting the input write address signal block address to a block address for a completely read block area so as to perform simultaneous read and write access even if the data read direction (order) of the frame memory is different from the data write direction. The address converter supplies the write block address to the frame memory. As a result, the data can be written in the completely read block.
申请公布号 JPH0563818(B2) 申请公布日期 1993.09.13
申请号 JP19840194395 申请日期 1984.09.17
申请人 CASIO COMPUTER CO LTD 发明人 HASEGAWA KOICHI;AOKI TAKASHI;KUDO HIDEKI
分类号 G06F3/12;G06F17/21;G06K15/00;G06K15/22;G06T1/60;G06T11/00;G09G5/36;H04N1/21;(IPC1-7):G06F3/12 主分类号 G06F3/12
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