| 摘要 |
The counter is able to set an initial value, and count afterward the setting value especially in the counter using a binary division circuit. The counter has the D-flipflop/binary division circuits (11,12,13) and the clock selection sections (14,15). The circuits (11-13) receive three data for setting the initial values (I&phgr; ,I1,I2) and a control signal for the input. According to the control signal, the D-flipflop/binary division circuit operates as the D-flipflop which outputs the data for setting the initial value or operates as the binary division circuit which outputs the count data (D&phgr;,D1,D2). The clock selection section selects a clock signal according to the control signal.
|
