发明名称 MEHTOD FOR CHECKING WRITING OF PROGRAMMABLE GATE ARRAY
摘要 PURPOSE:To provide a method for checking a simple writing of logic circuit data written in a programmable gate array. CONSTITUTION:When a predetermined logic circuit is written in a programmable gate array 1, a preset simple checking circuit is written separately from the logic circuit in it or a plurality of checking logic modules TM1-TMn to be added. After the predetermined logic circuit is written in the array 1, written states of the modules TM1-TMn are checked, thereby deciding whether the writing of the logic circuit of the array 1 is good or not.
申请公布号 JPH05235163(A) 申请公布日期 1993.09.10
申请号 JP19920035503 申请日期 1992.02.24
申请人 FUJITSU LTD 发明人 KITAYAMA SEIJI
分类号 G01R31/28;G06F11/22;H01L21/82 主分类号 G01R31/28
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