发明名称 FRAME SYNCHRONIZATION DETECTION CIRCUIT
摘要 PURPOSE:To realize the frame synchronization detection circuit detecting quickly the synchronization with respect to the frame synchronization detection circuit in digital communication. CONSTITUTION:This detection circuit is provided with a pattern detection circuit 10 detecting two frame patterns FA, FB from input data and generating timing signals A, B, a pulse generating circuit 20 generating the timing signals A, B of two frame patterns FA, FB, a pattern comparator circuit 30 comparing the timings of the timing signals A, B generated from the pattern detection circuit 10 and of the timing signals A, B generated from the pattern comparator circuit 30, a protection circuit 40 applying the prescribed number of protections to the output of the pattern comparator circuit 30 and a load control circuit 50 controlling a timing signal loaded to the pulse generating circuit 20, and the synchronization detection operation after detection of out of synchronism is started from any of the two frame patterns A, B.
申请公布号 JPH05235925(A) 申请公布日期 1993.09.10
申请号 JP19920030280 申请日期 1992.02.18
申请人 FUJITSU LTD 发明人 MASUDA HIDEYUKI;KOSUGI TORU
分类号 H04J3/06;H04J3/00;H04L7/08 主分类号 H04J3/06
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