发明名称 VALIDATION TECHNIQUE FOR INTEGRATED CIRCUIT MANUFACTURE
摘要 A method of making an integrated circuit involves first placing the digital information characterizing the circuit into two separate and different formats. The latter are then transmitted to the manufacturing plant where they are compared. The two formats are then used to form respective artworks depicting a mask for making the integrated circuit. The artworks are then compared. The integrated circuit is then built from the information of one of said formats and is compared with the information in the other format.
申请公布号 US3698072(A) 申请公布日期 1972.10.17
申请号 USD3698072 申请日期 1970.11.23
申请人 INTERN. BUSINESS MACHINES CORP. 发明人 JEFFREY G. KOENS;ROBERT D. MERILLAT
分类号 H01L27/02;(IPC1-7):H01L19/00 主分类号 H01L27/02
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