| 摘要 |
PURPOSE:To provide the timing recovery circuit for a digital signal receiver in which high speed locking is attained, timing jitter is reduced and a signal of a multilevel code transmission system is used for an input signal. CONSTITUTION:Since a timing when an input signal 4 crosses with plural reference levels is obtained by an identification circuit 7, the number of crossing with the reference levels is increased more than the case with reference zero- cross levels only and the phase-locking speed is increased. Furthermore, a reference level discrimination circuit 9 obtaining a new reference level corresponding to a transition of the input signal 4 based on data of the identification circuit 7, a 2nd identification circuit 10 obtaining a timing when a reference level obtained by the reference level discrimination circuit 9 and the input signal 4 are in crossing, and a phase comparator circuit 1 comparing phases by using the timing outputted from the identification circuit 10 are used to reduce timing jitter caused by the kind of transition of a multi-value code of the input signal 4. |
