| 摘要 |
A bias circuit for a complementary transistor power amplifier output stage which comprises a biasing transistor having its emitter connected to the base of one of the complementary transistors and its collector connected to the base of the other of the complementary transistors. A collector resistor is in circuit with the collector of the biasing transistor and with a source of biasing potential. The input signal to the amplifier is coupled to the emitter of the biasing transistor and to the base of one of the complementary transistors. In one embodiment, a resistive divider biases the base of the biasing transistor, while in another embodiment, the base of the biasing transistor is directly connected to the source of biasing potential.
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