| 摘要 |
<p>PURPOSE:To efficiently set wait time at a processor. CONSTITUTION:This circuit is provided with a wait generating circuit 1 to generate a wait signal 102 while receiving wait time information 101, delay circuit group 2 equipped with delay circuits 7, 8 and 9 to output a master clock 104 while delaying it for arbitrary time, system clock selecting circuit 3 to select one of the master clock 104 and clocks 105, 106 and 107 outputted from the delay circuit group 2 and to output that selected clock as a system clock 108, program counter 4, incrementer 5 to execute increment through the program counter 4 and the system clock 108, and instruction decoder 6 to decode a prescribed instruction and to output an instruction signal 101.</p> |
