| 摘要 |
PURPOSE:To achieve an erasure operation which does not cause any excess erasure in a one-cell one-stacked gate memory MOS Tr type E<2>PROM and to shorten the erasure time of the title memory device by a method wherein a source for each memory MOS Tr is connected to a bit line and a drain is connected to a common line. CONSTITUTION:A write operation is performed in the following manner: a negative voltage (e.g. -9V) is applied to a word line ML; a common line COM (i.e., a drain line D) is made open; a voltage of, e.g. +5V is applied to a bit line BL; and electrons are tunneled and injected into a source from a floating gate for a memory cell. A readout operation is performed in the following manner: the line COM is set to 0 V; the line BL (i.e., a source S) is set to, e.g. 1V; a voltage of +5 is applied to the ward line WL; and a channel current is detected. An erasure operation can be performed by two methods. In one method, the line COM is set to, e.g. 5V, the line BL (i.e., the source) is set to 0V, 10V is applied to the line ML, a corresponding channel current is made to flow and hot electrons are injected, by a tunneling effect, into the floating gate from the drain D. |
