| 摘要 |
PURPOSE:To provide the title manufacturing method of semiconductor device capable of attaining the offset length of a drain region in a TFT constantly at optimum value without depending upon the misalignment of lithography. CONSTITUTION:The impurities of gate electrode layers G05, G06 are diffused in a semiconductor layer wherein the concentration of the impurities doped on the gate electrode layers G05, G06 of a TFT is controlled and then the gate electrode layers G05, G06 are connected to the semiconductor layer through a contact hole 64 so as to form an impurity diffused layer in a drain region for the other gate electrode layers G05, G06 while controlling the offset length O. At this time such a TFT can be used as a load transistor of a SRAM. |
