| 摘要 |
PURPOSE:To attain high speed data transfer with respect to the data transfer device. CONSTITUTION:A discrimination circuit 4. detects a succeeding bit inverted 8 times after being synchronously with a PLL synchronizing signal as to each of parallel data D7-D0 synchronously with the PLL synchronizing signal as a head bit of valid data, detects a bit before a head bit of the valid data by 8-bits as a head bit of the valid data start signal and generates a new parallel data group synchronously with the valid data based on the head bit of the detected valid data and the head bit of the valid data start signal. Even when each of parallel data D7-D0 not synchronously with the valid data is transferred in parallel with synchronization, the parallel data group and the valid data are synchronized without converting each of parallel data D7-D0 to be transferred into serial data. |
