INTEGRATED CIRCUIT LAYOUT PATTERN GENERATOR,申请号JP19920039831-传众专利搜索

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发明名称	INTEGRATED CIRCUIT LAYOUT PATTERN GENERATOR
摘要
申请公布号	JPH05235166(A)	申请公布日期	1993.09.10
申请号	JP19920039831	申请日期	1992.02.26
申请人	NEC CORP	发明人	ITOU MAKIKO
分类号	H01L21/82;G06F17/50;(IPC1-7):H01L21/82;G06F15/60	主分类号	H01L21/82
代理机构		代理人
主权项
地址

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